1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to improvement of the operating characteristics of FETs, IGBTs and MCTs.
2. Background of the Invention
In an FET in which an N+ source region is spaced from an N type drift/drain region by a P type body region with an insulated gate electrode disposed over the P type body region and extending from the source region to the drift/drain region, a parasitic NPN bipolar transistor is disposed in parallel with the desired field effect transistor. A first main electrode is disposed in ohmic contact with the source and body regions and a second main electrode is disposed in ohmic contact with the drain region. In this parasitic bipolar transistor, the N type source region functions as an emitter, the P type body region functions as the base region and the N type drain region functions as the collector and the emitter/base function is shorted. During FET turn-off of an inductive load, this parasitic NPN transistor can become conductive and have a detrimental effect on the operation of the field effect transistor or result in its destruction. In circuits in which the body/drift region PN junction (an inherent diode) becomes forward biased, there is a substantial hole current in the P type body region extension beneath the source region. This current, in combination with the relative high resistance of that portion of the body region, can produce a sufficient voltage drop to forward bias the source/body junction far from the first main electrode contact which shorts that junction. When that portion of the source/body PN junction injects carriers, the NPN parasitic transistor becomes conductive, which can destroy the device. In power FETs, a large gain in this parasitic NPN transistor has an adverse effect on the ruggedness of the FET because the larger the gain of this NPN transistor, the smaller the current required to turn it on and the smaller the safe operating area of the FET is. The safe operating area is the combination of current and voltage which the FET can withstand during the process of turning off without destruction of the device. At a given voltage, increasing the current through the FET to more than the maximum SOA value for that voltage leads to breakdown of the device. Similarly, increasing the voltage at a fixed current level to more than the SOA maximum voltage for that current also leads to breakdown of the device which prevents the device from turning off. Such breakdown can also result in destruction of the device. For these reasons, it is considered desirable to minimize the gain of the parasitic NPN transistor in power FETs. The gain of this NPN transistor depends on the doping level of the P type body region. The higher the doping level of the P type body region, the lower is the gain of this NPN transistor. Consequently, in order to minimize the adverse effect of this parasitic NPN transistor, it is desirable to dope the body region as heavily P type as possible. Unfortunately, heavy doping of the body region has an adverse effect on the operation of the desired field effect transistor. That is, increasing the doping level of the P type body region increases the threshold voltage of the N type channel extending through the P type body region from the source to drain region, i.e. the gate voltage necessary to render that channel conductive to electrons.
It is known in the prior art to heavily dope the P type body region and to counter dope just the channel portion of the body region by implanting N type dopant material into the surface of the body region to reduce its net P type doping level to adjust the threshold voltage of the field effect transistor independent of the doping level of the P type body region.
The presence of this parasitic NPN bipolar transistor does not have any significant effect on the ON-state operation of the field effect transistor. It is only during turn-off of the field effect transistor in the presence of an inductive load or during turn-off of the inherent diode that this parasitic NPN bipolar transistor has an effect on the operating characteristics of the device. Thus, this parasitic bipolar transistor only affects the operating characteristics of a field effect transistor if that field effect transistor is a power device which will be operated near the limits of its safe operating area.
An insulated gate bipolar transistor (IGBT) is similar in structure to an FET, except that a P+ collector region is disposed between the N type drift region and second main electrode. Consequently, an IGBT contains a similar parasitic NPN bipolar transistor. However, this parasitic NPN transistor does not affect the SOA of the device because it is the lower or PNP transistor which limits device SOA. Rather, in the IGBT, this parasitic transistor affects the main current level at which the IGBT latches in the ON-state. The larger the gain of this parasitic NPN transistor, the lower the latching current of the IGBT becomes. As is well known, the IGBT is intended to be a non-latching device and, therefore, such decreased latching current is undesirable. Consequently, it is desirable to minimize the gain of the parasitic NPN transistor in an IGBT in order to maximize the latching current of the IGBT. The same techniques may be used to minimize the gain of the parasitic NPN transistor in an IGBT as are used in FETs. Thus, the only reason for reducing the gain of the parasitic NPN transistor in an IGBT is to increase latching current.
An MOS controlled thyristor (MCT) incorporates a field effect structure designed to carry current from the N type base region directly to the first power electrode to bypass the P type emitter/N type base region junction of the thyristor and thereby interrupt the regenerative action in the thyristor to turn it off. Introduction of this field effect structure creates what is in effect a field effect transistor of the N+ source region of the turn-off structure, the P type emitter region of the thyristor and the N type base region of the thyristor. This structure includes a parasitic NPN bipolar transistor. By analogy to the IGBT, decreasing the gain of that parasitic NPN bipolar transistor is expected to increase the latching current of the MCT, which is undesirable since the MCT is intended to latch on in the ON-state. Consequently, the prior art provides no reason to attempt to reduce the gain of this parasitic NPN bipolar transistor.
Consequently, the prior art provides no teaching or suggestion for heavily doping the portion of the P type emitter region of an MCT in the vicinity of the turn-off channel of the MOS structure in combination with counter doping of that channel. The prior art incentives for such structures in FETs or IGBTs are not applicable to MCTs because the problems that structure ameliorates in FETs and IGBT do not exist in the MCTs.
It has become desirable to operate circuits including MCTs at as high a frequency as possible, in such systems as dc-to-dc power converters. Consequently, new MCT structures which facilitate operation at higher frequencies are desirable.
With the advent of trench gate FETs and IGBTs, control of the gain of the parasitic NPN bipolar transistor has been one of the considerations in the trade-off decision as to whether to use a trench structure or a planar structure because ion implantation counter doping of the channel portion of the body or base region of a trench gate device is not possible because the trench walls are normally perpendicular to the major surface of the wafer whereby ion implantation ions are traveling parallel to the trench walls and thus do not implant in the body or base region. Since counter doping is not possible, a designer, in designing a trench gate FET or IGBT, must choose between a high threshold voltage with a low gain parasitic NPN transistor and a low threshold voltage with a high gain parasitic NPN transistor. Consequently, an improved structure for minimizing the gain of the parasitic NPN transistor in FETs and IGBTs, especially trench gate versions is needed, as is a method of providing such a structure.
While it is known that indium and aluminum are P type dopants, it is standard practice in the semiconductor industry to avoid using indium and aluminum as dopants in silicon because their small segregation coefficients lead to unpredictability of a process to obtain a desired structure. Use of boron as a P type dopant produces device structures and characteristics which are quite predictable. The reasons behind the essentially exclusive use of boron as a P type dopant are discussed in xe2x80x9cThe Theory and Practice of Microelectronicsxe2x80x9d by Sorab K. Ghandi published by John Wiley and Sons, especially in the xe2x80x9cChoice of p-type Impurityxe2x80x9d section. While there is much literature on the characteristics of boron and phosphorous as dopants in silicon, there is much less literature dealing with the use of indium and aluminum to create P type doped regions. An article entitled xe2x80x9cDiffusion of Indium in Silicon Inert and Oxidizing Ambientsxe2x80x9d, by D.A. Antoniadis et al., which appeared in the Journal of Applied Physics, Volume 53, No. 12, December 1982, pages 9214-9216 presents data on the diffusion characteristics of indium and concludes that indium has a segregation coefficient of 0.1. Both of these references are incorporated herein by reference.
Those skilled in the semiconductor art rely on established, controllable processes for the fabrication of devices because of their established, relatively high yields, rather than experimenting with processes which are known to be difficult to predict or control, unless there is a clear incentive for the use of the xe2x80x9cunpredictablexe2x80x9d process. There has been no such incentive for the use of indium or aluminum as dopants in silicon in the fabrication of field effect devices because of the availability and established techniques for controlling ion implantation of the counter dopant material in the channel portion of the body region to control the threshold voltage of the insulated gate structure in the presence of heavy body region dopant concentrations.
Accordingly, a primary object of the present invention is to provide an improved structure for controlling the threshold voltage of FETs and IGBTs having trench gates.
Another object of the present invention is to provide an MCT structure having a faster turn-off than prior art MCT structures.
Another object is to provide an improved method of fabricating FETs, IGBTs and MCTs.
In accordance with the above objects and others which will become apparent from the specification as a whole, including the drawings, an FET is provided with a heavily doped P type body region and a more lightly doped channel region by doping the body region with one or more of indium, aluminum and gallium or a combination of dopants including boron and one or more of indium, aluminum and gallium. Indium and aluminum are depleted in the body region adjacent the gate oxide because indium and aluminum both have small silicon/silicon dioxide segregation coefficients. The concentration of gallium is substantially reduced because of its higher diffusion rate in the oxide. The resulting structure is functionally equivalent to counter doping of the channel where only boron has been used to dope the base region. However, unlike counter doping, this technique is equally effective for trench gate structures and planar structures. Consequently, it is a substantial advance over the use of ion implantation counter doping since it provides independent control over body doping level and threshold voltage in trench gate devices.
Use of a combination of boron and one or more of aluminum, indium and gallium as the base dopant in an IGBT is similar in providing the same benefits provided by counter doping the channel portion of the base region.
We have found that in an MCT, providing a heavily doped P type emitter region along with a low threshold voltage channel in the MOS turn-off structure in that emitter region provides a substantial improvement in the MCT""s operating characteristics, in particular, by providing a much more rapid turn-off of the device upon application of a turn-off voltage to the insulated gate. This newly desirable structure may be provided either by doping the P type emitter region with a combination of boron and one or more of indium, aluminum and gallium or by counter doping the channel portion of that P type emitter region of a surface gate device to provide a low threshold voltage along with a heavy doping of the emitter region everywhere except in the channel itself.